1. Field of the Invention
The present invention relates to semiconductor devices having field effect transistors and, more specifically, to semiconductor devices having field effect transistors with higher degree of integration. The present invention has particular utility in the field of gate arrays.
2. Description of the Background Art
Recently, there have been various types of LSIs (Large Scale Integrated Circuits) for specific or dedicated use, and different products are provided for different users. In other words, small numbers of various types of products must be provided, and various different manufacturing processes have been needed to provide various types of products for various users. Consequently, when we consider mask patterns employed during the manufacturing processes, for example, various patterns must be designed and various masks must be prepared corresponding to various products. Therefore, the time for developing and designing one LSI becomes longer and the manufacturing cost thereof is increased.
In view of the foregoing, gate arrays are proposed and have been commercially available which enable manufacturing of various types of semiconductor devices by changing only some steps of the manufacturing process. A gate array comprises gates which are called elemental cells arranged regularly (in an array) on an LSI chip. It is a semi-custom LSI designed by making the best use of CAD with the design, development and manufacturing process of a custom LSI being standardized to a large extent. Although the chip size of the gate array is increased compared with a full-custom LSI, the time for development and the manufacturing cost thereof can be reduced. Therefore, the gate arrays have been continuously improved and developed to provide higher performance and functions from the first actual application in early 1970's. The gate array comprises semiconductor elements shown in FIG. 1 repeatedly arranged regularly, and the gate array realizes a desired function only by determining a wiring pattern in accordance with a logic circuit diagram. Therefore, the gate array enables reduction of the designing cost, greatly reducing the time required for development, and it is suitable for providing small numbers of various types of products.
FIG. 1 is a schematic prospective view of an n channel MOS transistor constituting the gate array. Referring to the figure, the MOS transistor Q.sub.0 comprises n type source 103 and drain 104 formed by diffusing n type impurities to a p type silicon substrate 2. A gate 106 formed of polysilicon is provided above a channel region 105 having a channel surface 105a formed between the source 103 and the drain 104, with a gate oxide layer (not shown) interposed therebetween. Other oxide layers and aluminum wirings are omitted in FIG. 1.
Since the n channel MOS transistor Q.sub.0 constituting the conventional gate array is structured as described above, an area S.sub.1 required for forming one n channel MOS transistor Q.sub.0 will be approximately EQU S.sub.1 =(L.sub.C +L.sub.D +L.sub.S).times.D.sub.1 ( 1)
as can be seen from FIG. 1. In the equation (1), the reference character L.sub.C represents a channel length, L.sub.D and L.sub.S represent the lengths of the drain 104 and the source 103 and D.sub.1 represents a channel width.
Therefore, in order to improve the degree of integration of the transistors in the gate array, that is, to improve the degree of integration of the n channel MOS transistors Q.sub.0 on the substrate 2, the n channel MOS transistor Q.sub.0 itself must be made compact by reducing the channel length L.sub.C, the lengths L.sub.D and L.sub.S of the drain 104 and the source 103 and the channel width D.sub.1 of each n channel MOS transistor Q.sub.0. However, when the n channel MOS transistor Q.sub.0 itself is made compact, the electrical characteristics of the transistor is degraded. For example, when the channel length L.sub.C is reduced to minimize the size of the n channel MOS transistor Q.sub.0, a short channel effect occurs, namely, the threshold voltage V.sub.TH of the MOS transistor reduces as the channel length becomes shorter. As the size of the MOS transistor is minimized, the MOS transistor shows undesired characteristics.
In order to solve the above described problem, one example of a semiconductor device capable of providing higher degree of integration without miniaturizing the transistor itself is disclosed in 1985, IEDM, Technical Digest, pp. 714-717, "A TRENCH TRANSISTOR CROSS-POINT DRAM CELL". FIG. 2 is a partial cross sectional view showing a cross sectional structure of such semiconductor device. Referring to FIG. 2, a dynamic memory cell is formed isolated by an isolating oxide layer 210 on a main surface of a p type silicon substrate 202. The dynamic memory cell comprises an n channel MOS transistor and a capacitor. The n channel MOS transistor has a drain 203 and a source 204 formed of n.sup.+ regions, a channel region 205 provided therebetween, and a gate electrode 206 formed on the channel region 205. The channel region 205 exists below a gate oxide layer 205a which is formed along a side wall portion of a trench formed on the main surface of the silicon substrate 202. The capacitor comprises a capacitor electrode 220 formed to be connected to the source 204 constituting the n channel MOS transistor and a capacitor oxide layer 230. The capacitor electrode 200 is formed of a polysilicon layer buried in the trench formed in the p type silicon substrate 202. The source 204 is provided in a ring around the capacitor electrode 220. The gate electrode 206 constituting the n channel MOS transistor is formed of polysilicon and it also serves as a word line.
In the dynamic memory cell shown in FIG. 2, a vertical n channel MOS transistor is formed on the side wall portion of the trench provided for the capacitor. By doing so, the horizontal area occupied by the n channel MOS transistor on the main surface of the substrate is reduced, but the transistor itself is not miniaturized and the performance of the transistor is maintained by forming the channel region on the side wall portion, for example.
However,, in this structure, the source 204 is formed by diffusing impurities included in the n.sup.+ type polysilicon, which is buried in the trench to form the capacitor electrode 200, by thermal processing. Therefore, it is difficult to apply the structure shown in this prior art to a structure of a MOS transistor with the source region not connected to an electrode or the like constituting the capacitor. In addition, an undercut must be provided between the n.sup.+ type polysilicon buried in the trench and the p type silicon substrate 202, and the polysilicon must be buried again in the undercut portion to form the source 204. This makes the manufacturing process complicated. The channel region 205 is provided on the side wall of the trench formed in the p type silicon substrate 202. Therefore, the channel length is controlled by changing the time of etching carried out to form the trench. Therefore, adjustment of the channel length is more difficult compared with a normal case in which the channel is adjusted by mask patterns.